Cirrus Logic EP73xx - Manual (Page 117)

EP7309/11/12 User’s Manual - DS508UM4 14-5
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Copyright Cirrus Logic, Inc. 2003
JTAG Interface
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This test is not intended to be used when LCD DMA accesses are enabled. This is due
to the fact that it is possible to have internal peripheral bus activity simultaneously
with a DMA transfer. This would cause bus contention to occur on the external bus.
The “Waited clock to CPU” is an internally ANDed source that generates the actual
CPU clock. Thus, it is possible to know exactly when the CPU is being clocked by
viewing this pin. The signals nFIQ and nIRQ are the two output signals from the
internal interrupt controller. They are input directly into the ARM720T processor.