Cirrus Logic EP73xx - Manual (Page 63)

EP7309/11/12 User’s Manual - DS508UM4 5-3
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Copyright Cirrus Logic, Inc. 2003
System Registers
55
5
Operational Overview
Most of the functions represented in the SYSCON and SYSFLG registers are either
described thoroughly in other chapters or require little explanation. Below is a
detailed explanation of those that do not get covered sufficiently elsewhere in this
manual.
Buzzer
The BUZ output pin on the EP73xx is intended as a signal source for a basic
annunciator. Two hardware sources and one software source are available for
controlling the frequency of the signal. In software mode, the
BUZ output reflects the
state of the BZTOG bit in SYSCON1. It is the responsibility of the software executing
on the EP73xx to toggle BZTOG at the desired frequency. Software mode can be used
to generate audio tones with a controlled volume by varying the duty cycle of the
pulse that BZTOG is fed. BZMOD must be cleared to enable the use of BZTOG.
Choices of hardware sources for BUZ include the timer clock and the output of on-
chip timer TC1. BUZFREQ selects between these two hardware sources. When
BUZFREQ is cleared, the buzzer is generated from the TC1 timer underflow bit. The
output changes every time the timer wraps around. The frequency depends on how
timer TC1 is configured. Prescale mode for timer TC1 provides the greatest flexibility
in the selection of a frequency for
BUZ . See Chapter 3 for a detailed description of
programming the timers. If BUZFREQ is set, then a 500 Hz internal timer is fed to
BUZ . Note that in the externally clocked 13 MHz mode, this clock will be 528 Hz
unless the OSTB bit (bit 12) in SYSCON2 is set.
BUZ is also used to created MCLK for external CODECs when the DAI is enabled. For
annunciator applications, BUZ for MCLK in the DAI must be disabled.
Debug Mode
Setting the debug mode bit in the SYSCON1 register allows internal memory accesses
that would normally not be represented to appear on the external memory bus. In
addition, the clock for this bus as well as the two interrupt signals that are generated
by the interrupt controller are output on Port E.
When in debug mode, nCS5 becomes the address strobe for the internal accesses in
addition to its usual function as an external memory strobe. External memory
accesses to the 0x5000.0000-0x5FFF.FFFF range will still cause
nCS5 to assert in
addition to internal memory accesses.
The nFIQ and nIRQ signals between the interrupt controller and the ARM720T core
will appear on Port E pins when debug mode is enabled.
PE1 will represent the state
of nIRQ, and PE2 will represent nFIQ. To aid in following memory accesses, PE0 will
output the internal bus clock. Using these extra signals requires that the data direction
bits for Port E pins
PE0 - PE2 must be set to output.