Interrupt mask register 3 (intmr3), Battery low end of interrupt (bleoi), Media change end of interrupt (mceoi) – Cirrus Logic EP73xx User Manual
Page 59: Tick end of interrupt (teoi), Tc1 end of interrupt (tc1eoi), End-of-interrupt locations
EP7309/11/12 User’s Manual - DS508UM4
4-13
Copyright Cirrus Logic, Inc. 2003
Interrupt Controller
44
4
Interrupt Mask Register 3 (INTMR3)
Address:
0x8000.2280, Read / Write
Definition:
This register contains the interrupt mask for the DAI interface. This
interrupt triggers the fast interrupt (FIQ) signal of the ARM720T
core.
Bit Descriptions:
DAIINT:
DAI interface interrupt. The cause must be determined by reading
the DAI status register. It is mapped to the FIQ interrupt on the
ARM720T processor.
End-Of-Interrupt Locations
The “End of Interrupt” locations that follow are written to after the appropriate
interrupt has been serviced. The write is performed to clear the interrupt status bit, so
other interrupts can be serviced. Any value may be written to these locations.
Battery Low End of Interrupt (BLEOI)
Address:
0x8000.0600
Definition:
A write to this location will clear the interrupt generated by a low
battery (falling edge of
BATOK
with
nEXTPWR
high).
Media Change End of Interrupt (MCEOI)
Address:
0x8000.0640
Definition:
A write to this location will clear the interrupt generated by a falling
edge of the
nMEDCHG
input pin.
Tick End of Interrupt (TEOI)
Address:
0x8000.0680
Definition:
A write to this location will clear the current pending tick interrupt
and tick watch dog interrupt.
TC1 End of Interrupt (TC1EOI)
Address:
0x8000.06C0
Definition:
A write to this location will clear the under flow interrupt generated
by TC1.
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RSVD
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RSVD
DAIINT