Cirrus Logic EP73xx - Manual (Page 94)

9-4 EP7309/11/12 User’s Manual - DS508UM4
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Copyright Cirrus Logic, Inc. 2003
LCD Interface
9
Latency and access times will need to be calculated prior to selecting an LCD panel to
guarantee available bandwidth for the rest of the system. It should be noted that the
refresh rate is not affected by the total number of pixels.
Gray Scale
The figure below shows the organization of the video map for all bits-per-pixel
combinations. As seen the in the diagram, the gray scale blocks represent the two 32-
bit palette registers. Each palette register represents eight 4-bit nibbles for a total of 16
nibbles.
Gray scale creates an intensity for each of the pixel values stored in memory. Four
bits-per-pixel corresponds to a theoretical color depth of 16. Two bits-per-pixel
corresponds to a color depth of four and so on. Since gray scale values 7 and 8 create
the same intensity, the actual color depth for 4bpp is 15. The effect is created by
simply controlling the amount of time the pixel remains on. See the Gray scale value
to Color Mapping diagram for more details.
An example of this would be the value 12, that is stored in a nibble in the framebuffer
memory. If the 4 bpp is programmed into the controller, the value 12 is mapped to the
LCD palette register for gray scale value for pixel value 12, assuming a one-to-one
correspondence between the number 12 in memory, and the intensity (Gray scale
value), this pixel will have a duty cycle of about 11/15 or will be lit approximately
73.3% of the time.
Programming the controller includes the following
• LCDCON: Configuration interface for a specific LCD panel
• PALLSW/PALMSW: Sets the palette registers
• FBADDR: Sets the start location in system memory for the LCD frame
buffer
• SYSCON1: LCDEN bit turns LCD controller on (enabled).
Note: LCD controller must not be enabled until the above registers are programmed.