Sram / expansion bus register descriptions, Memory configuration register 1 (memcfg1), Sram / expansion bus register descriptions -3 – Cirrus Logic EP73xx User Manual
Page 87: Memory configuration register 1 (memcfg1) -3, Table 8-2: bus width selection settings -3
EP7309/11/12 User’s Manual - DS508UM4
8-3
Copyright Cirrus Logic, Inc. 2003
SRAM/Expansion Bus Controller
88
8
SRAM / Expansion Bus Register Descriptions
Memory Configuration Register 1 (MEMCFG1)
Address:
0x8000.0180, Read / Write
Definition:
Each of the chip selects contain the same 8-bit programmable bit
fields that make up the entire configuration. The table below
describes each 0-7 bit configuration for all of the chip selects in
MEMCFG1 and MEMCFG2.
Bit Descriptions:
Bus Width[0:1]:The table below indicates what to program into the 2-bit field.
PE1
and
PE0
are examined at power-on-reset. Based on those
values, the Bus Width field values can be determined. This will
require examining the external hardware to know the default state
of each pin at power-on-reset.
Ex. If
PE1
and
PE0
are both low at
nPOR
, the bus width field
would then be 00 for the chip select to be programmed. This
assumes the external memory is 32 bits wide.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
nCS[3] Configuration
nCS[2] Configuration
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
nCS[1] Configuration
nCS[0] Configuration
7
6
5:2
1:0
CLKENB
SQAEN
Wait States Field
Bus width
Table 8-2: Bus Width Selection Settings
Bus Width Field
Expansion Transfer Mode
Port E bits 1,0 during
nPOR reset
00
32-bit wide bus access
Low, Low
01
16-bit wide bus access
Low, Low
10
8-bit wide bus access
Low, Low
11
Reserved
Low, Low
00
8-bit wide bus access
Low, High
01
Reserved
Low, High
10
32-bit wide bus access
Low, High
11
16-bit wide bus access
Low, High
00
16-bit wide bus access
High, Low