Cirrus Logic EP73xx - Manual (Page 113)

EP7309/11/12 User’s Manual - DS508UM4 14-1
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Copyright Cirrus Logic, Inc. 2003
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Chapter 14
14 JTAG Interface
Introduction
EmbeddedICE
®
is an extension to the architecture of the ARM family of processors,
and provides the ability to debug cores that are deeply embedded into systems. The
processor also has built-in test modes for functional testing of system clock and other
interfaces.
Features
• A set of extensions to the ARM core
• The EmbeddedICE macrocell, which provides external access to the
extensions
• The EmbeddedICE interface, which provides communication between the
host computer and the EmbeddedICE macrocell
• Debug Modes and Test Pins
Operational Overview
The ICEBreaker module consists of two real-time watchpoint units together with a
control and status register. One or both of the units can be programmed to halt the
execution of the instructions by the ARM processor. Execution is halted when either a
match occurs between the values programmed into the ICEBreaker and the values
currently appearing on the address bus, data bus, and the various control signals.
Any bit can be masked to remove it from the comparison. Either unit can be
programmed as a watchpoint (monitoring data accesses) or a breakpoint (monitoring
instruction fetches).
Using one of these watchpoint units, an unlimited number of software breakpoints
(in RAM) can be supported by substitution of the actual code.
Note: The EXTERN[1:0] signals from the ICEBreaker module are not wired out in this
device. This mechanism is used to allow watchpoints to be dependent on an
external event. This behavior can be emulated in software via the ICEBreaker
control registers.
A more detailed description is available in the ARM Software Development Toolkit User
Guide and Reference Manual. The ICEBreaker module and its registers are fully
described in the ARM7TDMI Data Sheet.