Cirrus Logic EP73xx - Manual (Page 114)

14-2 EP7309/11/12 User’s Manual - DS508UM4
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Copyright Cirrus Logic, Inc. 2003
JTAG Interface
14
Boundary Scan
IEEE 1149.1 compliant JTAG is provided with the EP73xx. The Table 14-1 shows the
instructions that are supported in the EP73xx.
The INTEST function will not be supported for the EP73XX.
Additional user-defined instructions exist, but these are not relevant to board-level
testing. For further information please refer to the ARM DDI 0087E ARM720T Data
Sheet.
As there are additional scan-chains within the ARM720T processor, it is necessary to
include a scan-chain select function — shown as SCAN_N in the table above. To select
a particular scan chain, this function must be input to the TAP controller, followed by
the 4-bit scan chain identification code. The identification code for the boundary scan
chain is 0011.
Note that it is only necessary to issue the SCAN_N instruction if the device is already
in the JTAG mode. The boundary scan chain is selected as the default on test-logic
reset and any of the system resets.
The contents of the device ID-register for the EP73xx are shown in the table below.
This is equivalent to 0x0F0F0F0F. Note this is the ID-code for the ARM720T processor.
Table 14-1: Instructions Supported in JTAG Mode
Instruction Code Description
EXTEST 0000
Places the selected scan
chain in test mode.
SCAN_N 0010
Connects the Scan Path
Register between TDI and
TDO
SAMPLE / PRELOAD 0011
This instruction is included
for product testing only and
should never be used.
IDCODE 1110
Connects the ID register
between TDI and TDO
BYPASS 1111
Connects a 1-bit shift
register bit TDI and TDO
Version Part number Manufacturer ID
0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1