GW Instek PPH-1503 User Manual
Page 124
PPH-1503 User Manual
124
0 Not used
1
Not used, returns “0”
1 Not used
2
Not used, returns “0”
2 Error Queue
4
Indicates that one or more errors are
stored in the error queue.
3 Questionable
Summary bit
8
One or more bits are set in the
questionable data register (for enabled
events).
4 Message
Available bit
16
Indicates that a message is available in
the output queue.
5 Standard Event
Summary bit.
32
Indicates that one or more bits are set
in the standard event register. (for
enabled events).
6 Master
Summary bit
64
Indicates that a summary bit is set in
the status byte register. (for enabled
summary bits)
7 Unused
128
Not used, returns “0”
The status byte condition register is cleared when one of the following occurs:
*CLS command is used to clear the status byte register.
The event registers are read
The status byte enable register is cleared when the following occurs:
When the *SRE 0 is command is executed.
Use the *STB? query to read the status byte register.
The *STB? query will return the contents of the status byte register as long as
the bit 6 (MSS) has been cleared.
Using the *OPC? query to place a signal in the output buffer.
In general it is best to use the Operation Complete Bit (bit 0) in the standard
event register to check to see if an operation/command has completed. After
executing the *OPC command, the OPC bit will be set to 1. If a command or
query is placed in the output buffer immediately before the *OPC command
is sent, the Operation Complete Bit can be used to determine when the
information can be used. However if too many commands/queries are