beautypg.com

Sample timeout, Sample dilution, Reagents – Luminex 100 IS Version 2.2 User Manual

Page 13: Kit instructions, Gating

background image

x

MAP

Technology

General Guidelines

PN 89-00002-00-032 Rev. A

7

Sample Timeout

Sample Timeout is the amount of time in seconds that the instrument
will read the sample to detect the specified number of events.

Specify a timeout for assay wells. If sufficient events are not
collected in the specified time, the Luminex 100 IS system logs an
error, flags the sample, and goes on to the next well. Set sample
timeout to several times longer than the expected read time of the
well. Set to zero to not use the timeout property.

Sample Dilution

Serum samples must be diluted at least 1:5 with reagents as part of
assay setup or as a final dilution step.

Reagents

Formulated reagents must be free of particulates other than
microspheres.

Kit Instructions

When you develop kit instructions, include:

Dilution and dilution reagent

Preparation steps, such as Sample Probe height adjustments that
need to accommodate the selection of plate type

XYP heater temperature setting

Information about assay controls and standard values for each
test in the assay as product lot information

Template name and version number in the kit instructions

Template provided on a 3½ diskette or CD

Gating

Determine the gating on the doublet discriminator channel for the
assay during development. The numeric values appear on the left-
hand side of the histogram. Use the numerical gate position
determined in development to set the gate location in the template.

Gating information may change with a new lot of microspheres.
Each time you receive a new lot of microspheres, re-evaluate them
with the current templates. If gating information changes, create a
new template that is the same as the current template but with a new
version number and new gating information. Gate positions are
dependent upon buffer composition. Any changes made to the
buffer composition in your assay may result in a different
optimal gate location.