Ds1874 sfp+ controller with digital ldd interface – Rainbow Electronics DS1874 User Manual
Page 49

DS1874
SFP+ Controller with Digital LDD Interface
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49
Table 01h, Register F8h: ALARM EN
3
POWER-ON
VALUE
00h
READ ACCESS
PW2 or (PW1 and RWTBL1C) or (PW1 and RTBL1C)
WRITE ACCESS
PW2 or (PW1 and RWTBL1C)
MEMORY TYPE
Nonvolatile (SEE)
F8h
TEMP HI
TEMP LO
VCC HI
VCC LO
MON1 HI
MON1 LO
MON2 HI
MON2 LO
BIT
7
BIT
0
Layout is identical to ALARM
3
in Lower Memory, Register 70h. Enables alarms to create TXFINT (Lower Memory,
Register 71h) logic. The MASK bit (Table 02h, Register 89h) determines whether this memory exists in Table 01h
or 05h.
BIT
7
TEMP HI:
0 = Disables interrupt from TEMP HI alarm.
1 = Enables interrupt from TEMP HI alarm.
BIT
6
TEMP LO:
0 = Disables interrupt from TEMP LO alarm.
1 = Enables interrupt from TEMP LO alarm.
BIT
5
VCC HI:
0 = Disables interrupt from VCC HI alarm.
1 = Enables interrupt from VCC HI alarm.
BIT
4
VCC LO:
0 = Disables interrupt from VCC LO alarm.
1 = Enables interrupt from VCC LO alarm.
BIT
3
MON1 HI:
0 = Disables interrupt from MON1 HI alarm.
1 = Enables interrupt from MON1 HI alarm.
BIT
2
MON1 LO:
0 = Disables interrupt from MON1 LO alarm.
1 = Enables interrupt from MON1 LO alarm.
BIT
1
MON2 HI:
0 = Disables interrupt from MON2 HI alarm.
1 = Enables interrupt from MON2 HI alarm.
BIT
0
MON2 LO:
0 = Disables interrupt from MON2 LO alarm.
1 = Enables interrupt from MON2 LO alarm.