IDEC MicroSmart - Manual (Page 202)

7: B ASIC I NSTRUCTIONS
7-18 « FC4A M ICRO S MART U SER ’ S M ANUAL »
SFR and SFRN (Forward and Reverse Shift Register)
The shift register consists of a total of 64 bits (all-in-one 10-I/O type CPU module) or 128 bits (other CPU modules) which
are allocated to R0 through R63 or R127, respectively. Any number of available bits can be selected to form a train of bits
which store on or off status. The on/off data of constituent bits is shifted in the forward direction (forward shift register) or
in the reverse direction (reverse shift register) when a pulse input is turned on.
Forward Shift Register (SFR)
When SFR instructions are programmed, two addresses are always required. The SFR instruction is entered, followed by a
shift register number selected from appropriate operand numbers. The shift register number corresponds to the first, or
head bit. The number of bits is the second required address after the SFR instruction.
The SFR instruction requires three inputs. The forward shift register circuit must be programmed in the following order:
reset input, pulse input, data input, and the SFR instruction, followed by the first bit and the number of bits.
Reset Input
The reset input will cause the value of each bit of the shift register to return to zero. Initialize pulse special internal relay,
M8120, may be used to initialize the shift register at start-up.
Pulse Input
The pulse input triggers the data to shift. The shift is in the forward direction for a forward shift register and in reverse for
a reverse shift register. A data shift will occur upon the leading edge of a pulse; that is, when the pulse turns on. If the pulse
has been on and stays on, no data shift will occur.
Data Input
The data input is the information which is shifted into the first bit when a forward data shift occurs, or into the last bit
when a reverse data shift occurs.
Note: When power is turned off, the statuses of all shift register bits are normally cleared. It is also possible to maintain the
statuses of shift register bits by using the Function Area Settings as required. See page 5-4.
Ladder Diagram
Structural Diagram
I2
I0
R0
Reset
Data
I1
Pulse
R1 R2 R3
Shift Direction
First Bit: R0 # of Bits: 4
I0
I1
SFR R0
4
I2
Reset
Pulse
Data
Instruction Data
LOD
LOD
LOD
SFR I0
I1
I2
R0
4
Program List
First Bit
# of Bits
Structural Diagram
I2
I0
R0
Reset
Data
I1
Pulse
R1 R2 R3
Shift Direction
# of Bits: 4
CPU Type All-in-One 10-I/O Others
First Bit R0 to R63 R0 to R127
# of Bits 1 to 64 1 to 128
Caution
• For restrictions on ladder programming of shift register instructions, see page 29-22.