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76 pattern size daca – 0x1dc (write) – Sundance SMT712 User Manual

Page 77

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User Manual SMT712

Page 77 of 89

Last Edited: 11/12/2012 10:36:00


4.6.1.1.76

Pattern size DACA – 0x1DC (write).

Pattern Size DACA – 0x1DC (write)

Byte

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

3

Pattern size[31:24]

Byte

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

2

Pattern size [23:16]

Byte

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

1

Pattern size [15:8]

Byte

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

0

Pattern size [7:0]


Pattern size has to be a multiple of 8. A size pattern of 8 means that 64 samples will
have to be loaded in memory and will be played back and sent out to the DAC.

4.6.1.1.77

Pattern size DACB – 0x1E0 (write).

Pattern Size DACB – 0x1E0 (write)

Byte

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

3

Pattern size[31:24]

Byte

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

2

Pattern size [23:16]

Byte

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

1

Pattern size [15:8]

Byte

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

0

Pattern size [7:0]


Pattern size has to be a multiple of 8. A size pattern of 8 means that 64 samples will
have to be loaded in memory and will be played back and sent out to the DAC.

4.6.2

DAC Synchronisation


The Digital to Analog converters used on the SMT712 have multiplexed inputs,
which means their input data rate is a fraction of the sampling rate. DACs have got
an internal clock divider in order to provide the data clock. These dividers can start
in any state at power up, which gives very little chance to have both DACs ‘in phase’
at this stage.
The synchronisation process is an iterative process. The SMT712 implements a
group of flip-flops to provide information on whether DAC data clocks are in phase
or not. In case they are not, the FPGA is capable of cancelling a certain number of
sampling clock cycles (7 – synch pulse) of DACA. Information on the clock phase
have to be collected again to check whether DACA and DACB data clocks are in
phase or not. The operation is repeated until they are in phase.
The SMT712 Demo application (SMT7002 package) implements this function.