Sundance SMT712 - Manual (Page 38)

User Manual SMT712 Page 38 of 89 Last Edited: 11/12/2012 10:36:00
DACB (MAX19692) Register 0x1 – Configuration Register – 0x48 (write)
Byte Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
0 Reserved Reserved Reserved Reserved Cal (DacB) Delay
(DacB)
RZ (DacB) RF (DacB)
Default ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’
DACB (MAX19692) Register 0x1 – Configuration Register – 0x48 (write)
Setting Bit 3 Description (Cal – DACB Output Resistance Calibration)
0 0 Output Resistors are un-calibrated.
1 1 Output Resistors are calibrated.
Setting Bit 2 Description (Delay – DACB Data Clock Delay Mode Input)
0 0 No Delay added.
1 1 Adds a delay of half of the input data period (2 DAC clock cycles).
Setting Bit 1 Description (RZ – DACB Return-to-Zero Mode select input)
0 0 Normal DAC mode of operation (NRZ – high dynamic range and output power in the first
Nyquist Zone).
1 1 Return-to-Zero mode of Operation (RZ – this mode trades-off SNR for improved gain
flatness in the first, second and third Nyquist zones)
Setting Bit 0 Description (RF – DACB Radio Frequence Mode Input)
0 0 NRZ or RZ DAC operation.
1 1 RF DAC operation (Provides higher SNR and dynamic performance in the second and
third Nyquist Zone).
4.6.1.1.5 DACA and B data source selection – 0x4C (write).
DACA and B data source selection – 0x4C (write)
Byte Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
0 Reserved DACB data source
selection
DACA data source
selection
Default ‘0000’ ‘00’ ‘00’
DACA and B data source selection – 0x4C (write)
Setting Bit 3..2 Description (DACB data source selection)
0 ‘00’ All data lines are assigned with logical ‘0’.
1 ‘01’ Samples routed from the SHB2 to the DACB. This only applies when SHB2 is fitted on the
board (non-PCI versions of the board).
2 ‘10’ Samples routed from the DDS (FPGA) to the DACB.
3 ‘11’ Samples routed from the DDR2 memory to the DACB.
Setting Bit 1..0 Description (DACA data source selection)
0 ‘00’ All data lines are assigned with logical ‘0’.
1 ‘01’ Samples routed from the SHB1 to the DACA.
2 ‘10’ Samples routed from the DDS (FPGA) to the DACA.
3 ‘11’ Samples routed from the DDR2 memory to the DACA.
4.6.1.1.6 Clock Generator (AD9516-2) Register 0x00 – Serial Port
Configuration – 0xC0 (write).