Sundance SMT712 - Manual (Page 19)

User Manual SMT712 Page 19 of 89 Last Edited: 11/12/2012 10:36:00
by the SMT6002. Storing a new bitstream at location 1 (User Bitstream 0) will only
require from the user to select the file (.bit for instance) and to press the ‘Comit’
button. The advanced tab offers more options such as a full erase or a partial erase
of the flash memory. None of them should be required in normal mode of operation.
Note that a full erase will erase the entire contents of the flash including the default
firmware and that it can take up to 3-4 minutes. The partial erase will erase the User
bitstreams only.
4.5.4
DDR2 Memory
Two banks of DDR2 memory are available on the SMT712, directly connected to the
FPGA. Interfaces are part of the FPGA design. Each bank is 64-bit wide and 128-Meg
deep, so each bank can store up to 1 Giga bytes of samples. Each memory bank is
dedicated to one DAC. Not all bits are used in the memory are 4 12-bit samples are
stored in a 64-bit word.
In the standard firmware provided with the board, both DDR2 interfaces are clocked
at 312MHz in order to be able to play back a pattern from the memory to match the
full DAC sampling rate.
4.5.5
Clock circuitry
An on-board PLL+VCO chip ensure a stable fixed sampling frequency (maximum
rate, i.e. 2300MHz), in order for the board to be used as synthesizer without the
need of external clock signal. The PLL will be able to lock the VCO either on the on-
board 10MHz PXI reference or the 100MHz PXI express reference or on an external
reference signal. The sampling clock for the converters can be either coming from
the PLL+VCO chip or from an external source. The chip used is a part from Analog
Devices, the AD9516-2. The reference used for locking the VCO is output on a
connector available on the front panel.
The selection Internal/External clock is made via a bit in the control register. The
same applies to the selection of the reference clock.
Below is a block diagram of the clock circuitry: