Sundance SMT712 - Manual (Page 44)

User Manual SMT712 Page 44 of 89 Last Edited: 11/12/2012 10:36:00
34 100010 DYN REF2 clock (N/A in differential mode).
33 100001 DYN REF1 clock (differential reference when in differential mode).
32 100000 LVL Ground (dc).
0xxxxx LVL Ground (dc); for all other cases of 0XXXXX not specified above. The selections that
follow are the same as REFMON.
6 000110 DYN PFD down pulse.
5 000101 DYN PFD up pulse.
4 000100 DYN Prescaler output.
3 000011 DYN A divider output.
2 000010 DYN R divider output (after the delay).
1 000001 DYN N divider output (after the delay).
0 000000 LVL Ground (dc).
Setting Bit 1..0 Description (Antibacklash Pulse Width)
3 11 2.9ns.
2 10 6.0ns.
1 01 1.3ns.
0 00 2.9ns.
LVL stands for level and DYN for dynamic.
4.6.1.1.16 Clock Generator (AD9516-2) Register 0x18 – PLL Control
3 – 0xE8 (write).
Clock Generator (AD9516-2) Register 0x18 – PLL Control 3 – 0xE8 (write)
Byte Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
0
Reserved Lock Detect Counter
Digital
Lock
Detect
Window
Disable
Digital
Lock
Detect
VCO Calibration
Divider
VCO Cal
now
Default ‘0’ ‘00’ ‘0’ ‘0’ ‘11’ ‘0’
Clock Generator (AD9516-2) Register 0x18 – PLL Control 3 – 0xE8 (write)
Setting Bit 3 Description (Lock Detect Counter)
3 11 255
2 10 64
1 01 16
0 00 5
Setting Bit 3 Description (Digital Lock Detect Window)
0 0 high range.
1 1 low range.
Setting Bit 2 Description (Disable Digital Lock Detect)
0 0 normal lock detect operation.
1 1 disable lock detect.
Setting Bit 1 Description (VCO Calibration Divider)
3 11 16 (default)
2 10 8