Sundance SMT712 - Manual (Page 37)

User Manual SMT712 Page 37 of 89 Last Edited: 11/12/2012 10:36:00
0 0 Normal Mode of Operation.
1 1 DCM gets reset (Auto-Clear)
Setting Bit 25 Description Force DACB DCM to Reset (Auto-Clear).
0 0 Normal Mode of Operation.
1 1 DCM gets reset (Auto-Clear)
Setting Bit 26 Description DACA sampling clock cancel cycle.
0 0 Normal Mode of Operation.
1 1 Cancels 7 clock cycles (of sampling clock) on DACA. This is used in the process of
synchronising DACs.
Setting Bit 30 Description – DDS / DDR2 Pattern Generator Start_nStop
0 0 The DDS/DDR2 Pattern Generator implemented in the FPGA is not running (default).
1 1 The DDS/DDR2 Pattern Generator starts running (after relevant parameter have been
loaded).
4.6.1.1.3 DACA (MAX19692) Register 0x1 – Configuration Register
– 0x44 (write).
DACA (MAX19692) Register 0x1 – Configuration Register – 0x44 (write)
Byte Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
0 Reserved Reserved Reserved Reserved Cal (DacA) Delay
(DacA)
RZ (DacA) RF (DacA)
Default ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’
DACA (MAX19692) Register 0x1 – Configuration Register – 0x44 (write)
Setting Bit 3 Description (Cal – DACA Output Resistance Calibration)
0 0 Output Resistors are un-calibrated.
1 1 Output Resistors are calibrated.
Setting Bit 2 Description (Delay – DACA Data Clock Delay Mode Input)
0 0 No Delay added.
1 1 Adds a delay of half of the input data period (2 DAC clock cycles).
Setting Bit 1 Description (RZ – DACA Return-to-Zero Mode select input)
0 0 Normal DAC mode of operation (NRZ – high dynamic range and output power in the first
Nyquist Zone).
1 1 Return-to-Zero mode of Operation (RZ – this mode trades-off SNR for improved gain
flatness in the first, second and third Nyquist zones)
Setting Bit 0 Description (RF – DACA Radio Frequence Mode Input)
0 0 NRZ or RZ DAC operation.
1 1 RF DAC operation (Provides higher SNR and dynamic performance in the second and
third Nyquist Zone).
4.6.1.1.4 DACB (MAX19692) Register 0x1 – Configuration Register
– 0x48 (write).