Sundance SMT712 - Manual (Page 73)

User Manual SMT712 Page 73 of 89 Last Edited: 11/12/2012 10:36:00
0 The Temperature is coded on 10 bits.
4.6.1.1.68 System Monitor – FPGA Core Voltages – 0x1C4 (read).
Offset 0x0400 – System Monitor – FPGA Core Voltages – 0x1C4 (read).
Byte Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
3 Reserved Maximum Vccint[9:4]
Default ‘00’ ‘000000’
2 Maximum Vccint[3:0] Minimum Vccint [9:6]
Default ‘0000’ ‘0000’
1 Minimum Vccint [5:0] Current Vccint [9:8]
Default ‘000000’ ‘00’
0 Current Vccint [7:0]
Default ‘00000000’
Offset 0x0400 – System Monitor – FPGA Core Voltages – 0x1C4 (read).
Setting Bit 29..20 Maximum FPGA Vccint (measured)
2 The Voltage is coded on 10 bits.
Setting Bit 19..10 Minimum FPGA Vccint (measured)
1 The Voltage is coded on 10 bits.
Setting Bit 9..0 Current FPGA Vccint (measured)
0 The Voltage is coded on 10 bits.
4.6.1.1.69 System Monitor – FPGA core voltage thresholds – 0x1C4
(write).
Offset 0x0400 – System Monitor – FPGA core voltage thresholds – 0x1C4 (write).
Byte Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
3 Reserved
Default ‘00000000’
2 Reserved Vccint upper threshold[9:6]
Default ‘0000’ ‘0000’
1 Vccint upper threshold[5:0] Vccint lower
threshold[9:8]
Default ‘000000’ ‘00’
0 Vccint lower threshold[7:0]
Default ‘00000000’
Offset 0x0400 – System Monitor – FPGA core voltage thresholds – 0x1C4 (write).
Setting Bit 19..10 FPGA Core voltage upper threshold
1 The Voltage is coded on 10 bits.
Setting Bit 9..0 FPGA Core voltage lower threshold
0 The Voltage is coded on 10 bits.