Sundance SMT712 - Manual (Page 31)

User Manual SMT712 Page 31 of 89 Last Edited: 11/12/2012 10:36:00
0x138 Clock Generator (AD9516-2) register 0xF0 – OUT0 Read-back (FPGA Register) Clock Generator
(AD9516-2) register 0xF0 – OUT0
0x13C Clock Generator (AD9516-2) register 0xF1 – OUT1 Read-back (FPGA Register) Clock Generator
(AD9516-2) register 0xF1 – OUT1
0x140 Clock Generator (AD9516-2) register 0xF2 – OUT2 Read-back (FPGA Register) Clock Generator
(AD9516-2) register 0xF2 – OUT2
0x144 Clock Generator (AD9516-2) register 0xF3 – OUT3 Read-back (FPGA Register) Clock Generator
(AD9516-2) register 0xF3 – OUT3
0x148 Clock Generator (AD9516-2) register 0xF4 – OUT4 Read-back (FPGA Register) Clock Generator
(AD9516-2) register 0xF4 – OUT4
0x14C Clock Generator (AD9516-2) register 0xF5 – OUT5 Read-back (FPGA Register) Clock Generator
(AD9516-2) register 0xF5 – OUT5
0x150 Clock Generator (AD9516-2) register 0x140 –
OUT6 Read-back (FPGA Register) Clock Generator
(AD9516-2) register 0x140 – OUT6
0x154 Clock Generator (AD9516-2) register 0x141 –
OUT7 Read-back (FPGA Register) Clock Generator
(AD9516-2) register 0x141 – OUT7
0x158 Clock Generator (AD9516-2) register 0x142 –
OUT8 Read-back (FPGA Register) Clock Generator
(AD9516-2) register 0x142 – OUT8
0x15C Clock Generator (AD9516-2) register 0x143 –
OUT9 Read-back (FPGA Register) Clock Generator
(AD9516-2) register 0x143 – OUT9
0x160 Clock Generator (AD9516-2) register 0x190 –
Divider0 Read-back (FPGA Register) Clock Generator
(AD9516-2) register 0x190 – Divider0
0x164 Clock Generator (AD9516-2) register 0x191 –
Divider0 Read-back (FPGA Register) Clock Generator
(AD9516-2) register 0x191 – Divider0
0x168 Clock Generator (AD9516-2) register 0x192 –
Divider0 Read-back (FPGA Register) Clock Generator
(AD9516-2) register 0x192 – Divider0
0x16C Clock Generator (AD9516-2) register 0x193 –
Divider1 Read-back (FPGA Register) Clock Generator
(AD9516-2) register 0x193 – Divider1
0x170 Clock Generator (AD9516-2) register 0x194 –
Divider1 Read-back (FPGA Register) Clock Generator
(AD9516-2) register 0x194 – Divider1
0x174 Clock Generator (AD9516-2) register 0x195 –
Divider1 Read-back (FPGA Register) Clock Generator
(AD9516-2) register 0x195 – Divider1
0x178 Clock Generator (AD9516-2) register 0x196 –
Divider2 Read-back (FPGA Register) Clock Generator
(AD9516-2) register 0x196 – Divider2
0x17C Clock Generator (AD9516-2) register 0x197 –
Divider2 Read-back (FPGA Register) Clock Generator
(AD9516-2) register 0x197 – Divider2
0x180 Clock Generator (AD9516-2) register 0x198 –
Divider2 Read-back (FPGA Register) Clock Generator
(AD9516-2) register 0x198 – Divider2
0x184 Clock Generator (AD9516-2) register 0x199 –
Divider3 Read-back (FPGA Register) Clock Generator
(AD9516-2) register 0x199 – Divider3
0x188 Clock Generator (AD9516-2) register 0x19A –
Divider3 Read-back (FPGA Register) Clock Generator
(AD9516-2) register 0x19A – Divider3
0x18C Clock Generator (AD9516-2) register 0x19B –
Divider3 Read-back (FPGA Register) Clock Generator
(AD9516-2) register 0x19B – Divider3
0x190 Clock Generator (AD9516-2) register 0x19C –
Divider3 Read-back (FPGA Register) Clock Generator
(AD9516-2) register 0x19C – Divider3
0x194 Clock Generator (AD9516-2) register 0x19D –
Divider3 Read-back (FPGA Register) Clock Generator
(AD9516-2) register 0x19D – Divider3
0x198 Clock Generator (AD9516-2) register 0x19E –
Divider4 Read-back (FPGA Register) Clock Generator
(AD9516-2) register 0x19E – Divider4
0x19C Clock Generator (AD9516-2) register 0x19F –
Divider4 Read-back (FPGA Register) Clock Generator
(AD9516-2) register 0x19F – Divider4
0x1A0 Clock Generator (AD9516-2) register 0x1A0 –
Divider4 Read-back (FPGA Register) Clock Generator
(AD9516-2) register 0x1A0 – Divider4