Sundance SMT712 - Manual (Page 3)

User Manual SMT712 Page 3 of 89 Last Edited: 11/12/2012 10:36:00
Table of Contents
1 Introduction ........................................................................................................................ 8
2 Related Documents........................................................................................................... 9
3 Acronyms, Abbreviations and Definitions..............................................................10
3.1 Acronyms and Abbreviations ...................................................................................10
4 Functional Description ..................................................................................................10
4.1 General Block Diagram...............................................................................................10
4.2 Block Diagram – Standard SMT712 (PXIe)..............................................................11
4.3 Block Diagram – SMT712-HYBRPXI32 (option 32-bit PXI) ..................................12
4.4 Block Diagram – SMT712-CPCI32 (Option 32-bit PCI).........................................13
4.5 Module Description.....................................................................................................13
4.5.1 DACs..........................................................................................................................13
4.5.2 FPGA ..........................................................................................................................14
4.5.2.1 General Description......................................................................................14
4.5.2.2 Resources used – XCV5FX70T....................................................................14
4.5.2.3 Resources used – XCV5FX100T. ................................................................15
4.5.3 Configuration (CPLD+Flash).................................................................................17
4.5.4 DDR2 Memory .........................................................................................................19
4.5.5 Clock circuitry .........................................................................................................19
4.5.6 Data (samples) path / Data storage....................................................................20
4.5.7 PXI Express Bus .......................................................................................................21
4.5.8 SHB connector .........................................................................................................23
4.5.9 External Trigger. .....................................................................................................23
4.5.10Power dissipation ...................................................................................................24
4.5.11JTAG ..........................................................................................................................24
4.5.12PXI Express Hybrid Connectors...........................................................................26
4.6 FPGA Design .................................................................................................................28
4.6.1 Control Registers ....................................................................................................29
4.6.1.1 Register Descriptions ...................................................................................32
4.6.1.1.1 General Control Register – 0x08 (read-only). ..................................32
4.6.1.1.2 Set Control Register – 0x10 (write). ...................................................35
4.6.1.1.3 DACA (MAX19692) Register 0x1 – Configuration Register – 0x44
(write). 37
4.6.1.1.4 DACB (MAX19692) Register 0x1 – Configuration Register – 0x48
(write). 37
4.6.1.1.5 DACA and B data source selection – 0x4C (write). ........................38
4.6.1.1.6 Clock Generator (AD9516-2) Register 0x00 – Serial Port
Configuration – 0xC0 (write)...................................................................................38
4.6.1.1.7 Clock Generator (AD9516-2) Register 0x04 – Read-back Control –
0XC4 (write). ...............................................................................................................39
4.6.1.1.8 Clock Generator (AD9516-2) Register 0x10 – PFD and Charge
Pump – 0xC8 (write)..................................................................................................39
4.6.1.1.9 Clock Generator (AD9516-2) Register 0x11 – R Counter – 0xCC
(write). 40