Sundance SMT712 User Manual
Page 69
User Manual SMT712
Page 69 of 89
Last Edited: 11/12/2012 10:36:00
Clock Generator (AD9516-2) Register 0x19E – Divider4 – 0x198 (write)
Setting
Bit 7..4
Description (Divider 4.1 Low Cycles)
0
Number of clock cycles of the divider input during which divider output stays low.
Setting
Bit 3..0
Description (Divider 4.1 High Cycles)
0
Number of clock cycles of the divider input during which divider output stays high.
4.6.1.1.60
Clock Generator (AD9516-2) Register 0x19F – Divider4 –
0x19C (write).
Clock Generator (AD9516-2) Register 0x19F – Divider4 – 0x19C (write)
Byte
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
Phase Offset Divider 4.2
Phase Offset Divider 4.1
Default
‘0000’
‘0000’
Clock Generator (AD9516-2) Register 0x19F – Divider4 – 0x19C (write)
Setting
Bit 7..4
Description (Phase Offset Divider 4.2)
0
Phase Offset.
Setting
Bit 3..0
Description (Phase Offset Divider 4.1)
0
Phase Offset.
4.6.1.1.61
Clock Generator (AD9516-2) Register 0x1A0 – Divider4 –
0x1A0 (write).
Clock Generator (AD9516-2) Register 0x1A0 – Divider4 – 0x1A0 (write)
Byte
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
Divider 4.2 Low Cycles
Divider 4.2 High Cycles
Default
‘0001’
‘0001’
Clock Generator (AD9516-2) Register 0x1A0 – Divider4 – 0x1A0 (write)
Setting
Bit 7..4
Description (Divider 4.2 Low Cycles)
0
Number of clock cycles of the divider input during which divider output stays low.
Setting
Bit 3..0
Description (Divider 4.2 High Cycles)
0
Number of clock cycles of the divider input during which divider output stays high.
4.6.1.1.62
Clock Generator (AD9516-2) Register 0x1A1 – Divider 4 –
0x1A4 (write).
Clock Generator (AD9516-2) Register 0x1A1 – Divider 4 – 0x1A4 (write)
Byte
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
Reserved
Bypass
Divider
3.2
Bypass
Divider
3.1
Divider 3
Nosync
Divider 3
Force High
Start High
Divider
3.2
Start High
Divider
3.1
Default
‘00’
‘0’
‘0’
‘0’
‘0’
‘0’
‘0’