Sundance SMT712 - Manual (Page 65)

User Manual SMT712 Page 65 of 89 Last Edited: 11/12/2012 10:36:00
4.6.1.1.50 Clock Generator (AD9516-2) Register 0x195 – Divider1 –
0x174 (write).
Clock Generator (AD9516-2) Register 0x195 – Divder1 – 0x174 (write)
Byte Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
0
Reserved
Divider
Direct to
Output
Divider
DCCOFF
Default ‘000000’ ‘0’ ‘0’
Clock Generator (AD9516-2) Register 0x195 – Divder1 – 0x174 (write)
Setting Bit 1 Description (Divider Direct to Output)
0 0 VCO calibration not finished.
1 1 VCO calibration finished.
Setting Bit 0 Description (Divider DCCOFF)
0 0 not in holdover.
1 1 holdover state active.
4.6.1.1.51 Clock Generator (AD9516-2) Register 0x196 – Divider2 –
0x178 (write).
Clock Generator (AD9516-2) Register 0x196 – Divider2 – 0x178 (write)
Byte Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
0 Divider Low Cycles Divider High Cycles
Default ‘0000’ ‘0000’
Clock Generator (AD9516-2) Register 0x196 – Divider2 – 0x178 (write)
Setting Bit 7..4 Description (Divider Low Cycles)
0 Number of clock cycles of the divider input during which divider output stays low.
Setting Bit 3..0 Description (Divider High Cycles)
0 Number of clock cycles of the divider input during which divider output stays high.
4.6.1.1.52 Clock Generator (AD9516-2) Register 0x197 – Divider2 –
0x17C (write).
Clock Generator (AD9516-2) Register 0x197 – Divider2 – 0x17C (write)
Byte Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
0 Divider
bypass
Divider
Nosync Divider
Force
High
Divider
Start High
Divider Phase Offset
Default ‘1’ ‘0’ ‘0’ ‘0’ ‘0000’