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Sundance SMT712 User Manual

Page 29

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User Manual SMT712

Page 29 of 89

Last Edited: 11/12/2012 10:36:00



4.6.1

Control Registers

The write packets must contain the address where the data must be written to and
the read packets must contain the address where the required data must be read.
The following figure shows the memory map for the writable and readable registers
on the SMT712.

The access to a specific register is made by reading or writing to the address:

Address from Host = Offset + Register Address

Offset

Description.

0x0000

SMT7xx Boards common registers (Reboot, global reset).

0x0400

SMT712 Registers (DACs, Clock and control).

0x0800

DACa data channel (Xlink 1)

0x0C00

DACb data channel (Xlink 2)

0x1000

Table of Contents (see Xlink Specifications for more details).

0x1400

Flash memory for bitstream storage.

0x2400

Event Block


Offset 0x0000 – SMT7xx Common Registers.

Register
Address

Writable Registers

Readable Registers

0x04

Global Reset (bit31).

Reserved.

0x80

Reconfiguration – Bitstream number.

Reserved.

Offset 0x0400 – SMT712 Registers.

Register
Address

Writable Registers

Readable Registers

0x08

Reserved.

General Control register.

0x10

Set Control Register.

Reserved.

0x20

Clear Control Register.

Reserved.

0x24

Reserved

Board Name and Version.

0x40

Reserved.

Firmware Version and Revision Numbers.

0x44

DACA (MAX19692) Register 0x1.

Read-back (FPGA Register) DACA (MAX19692)
Register 0x1.

0x48

DACB (MAX19692) Register 0x1.

Read-back (FPGA Register) DACB (MAX19692)
Register 0x1.

0x4C

DACA and B data source selection

Read-back (FPGA Register) DACA and B data
source selection

0xC0

Clock Generator (AD9516-2) register 0x00 – Serial
Port Configuration

Read-back (FPGA register) Clock Generator
(AD9516-2)

register

0x00

Serial

Port

Configuration

0xC4

Clock Generator (AD9516-2) register 0x04 – Read-
back control

Read-back (FPGA Register) Clock Generator
(AD9516-2) register 0x04 – Read-back control

0xC8

Clock Generator (AD9516-2) register 0x10 – PDF
and Charge Pumpe

Read-back (FPGA Register) Clock Generator
(AD9516-2) register 0x10 – PDF and Charge
Pumpe