Sundance SMT712 - Manual (Page 16)

User Manual SMT712 Page 16 of 89 Last Edited: 11/12/2012 10:36:00
Number using O6 output only: 204
Number using O5 output only: 20
Number using O5 and O6: 84
Number used as Shift Register: 182
Number using O6 output only: 182
Number used as exclusive route-thru: 207
Number of route-thrus: 892
Number using O6 output only: 698
Number using O5 output only: 193
Number using O5 and O6: 1
Slice Logic Distribution:
Number of occupied Slices: 8,232 out of 16,000 51%
Number of LUT Flip Flop pairs used: 24,867
Number with an unused Flip Flop: 4,564 out of 24,867 18%
Number with an unused LUT: 10,201 out of 24,867 41%
Number of fully used LUT-FF pairs: 10,102 out of 24,867 40%
Number of unique control sets: 1,027
Number of slice register sites lost
to control set restrictions: 2,077 out of 64,000 3%
A LUT Flip Flop pair for this architecture represents one LUT paired with
one Flip Flop within a slice. A control set is a unique combination of
clock, reset, set, and enable signals for a registered element.
The Slice Logic Distribution report is not meaningful if the design is
over-mapped for a non-slice resource or if Placement fails.
OVERMAPPING of BRAM resources should be ignored if the design is
over-mapped for a non-BRAM resource or if placement fails.
IO Utilization:
Number of bonded IOBs: 536 out of 640 83%
Number of LOCed IOBs: 535 out of 536 99%
IOB Flip Flops: 726
IOB Master Pads: 97
IOB Slave Pads: 97
Number of bonded IPADs: 10
Number of LOCed IPADs: 2 out of 10 20%
Number of bonded OPADs: 8
Specific Feature Utilization:
Number of BlockRAM/FIFO: 45 out of 228 19%
Number using BlockRAM only: 29
Number using FIFO only: 16
Total primitives used:
Number of 36k BlockRAM used: 10
Number of 18k BlockRAM used: 22
Number of 36k FIFO used: 14
Number of 18k FIFO used: 2
Total Memory used (KB): 1,296 out of 8,208 15%
Number of BUFG/BUFGCTRLs: 24 out of 32 75%
Number used as BUFGs: 24
Number of IDELAYCTRLs: 8 out of 22 36%
Number of BUFDSs: 1 out of 8 12%
Number of BUFIOs: 16 out of 80 20%
Number of DCM_ADVs: 8 out of 12 66%
Number of LOCed DCM_ADVs: 8 out of 8 100%
Number of GTX_DUALs: 2 out of 8 25%
Number of LOCed GTX_DUALs: 2 out of 2 100%
Number of PCIEs: 1 out of 3 33%
Number of LOCed PCIEs: 1 out of 1 100%
Number of PLL_ADVs: 1 out of 6 16%