Artesyn ATCA-8330 Installation and Use (April 2015) - Manual (Page 89)

BIOS
ATCA-8330 Installation and Use (6806800S82B) 89
4.7.8.1 Independent Channel Mode
In independent mode, all four channels are operating independently. The ECC code appears in
each independent channel. Failure of the DRAM can be corrected. The correction capabilities in
independent mode are:
 Correction of any x4 DRAM device failure.
 Detection of 99.986% of all single bit failures that occur in addition to an x4 DRAM failure.
 Detection of any 2-bit uncorrectable errors.
4.7.8.2 Mirrored Channel Mode
The Integrated Memory Controller supports mirroring across channels. DIMM organization in
each slot of one channel must be identical to the DIMM in the corresponding slot of the other
channel. When mirroring is enabled, the memory image in Channel 0 is maintained similar to
Channel 1. DIMMs and Channel 2 is maintained to Channel3 DIMMs. Uncorrectable errors are
logged and signaled as correctable, but change the channel state to "Disabled", and the
working partner to "Redundancy Loss".
4.7.8.3 Lockstep Channel Mode
The Lockstep configuration requires all memory channels equipped with the same DIMMs. The
ECC DRAM on each DIMM is mapped in to two adjacent symbols so that any failure of the DRAM
can be corrected. The correction capabilities in lockstep mode are:
 Correction of any x4 or x8 DRAM device failure.
 Detection of 99.986% of all single bit failures that occur in addition to an x8 DRAM failure.
 The Memory Controller will detect a series of failures on a specific DRAM and use this
information in addition to the information provided by the code to achieve 100% detection
of these cases.
 Detection of all permutations of 2 x4 DRAM failures.
4.8 Restoring BIOS Default Settings
The blade provides an on-board configuration switch that allows to load BIOS settings from the
DEFAULT area of the IPMI Boot Parameters. In order to restore the BIOS default settings using
this switch, proceed as follows: