Artesyn ATCA-8330 Installation and Use (April 2015) - Manual (Page 109)

Functional Description
ATCA-8330 Installation and Use (6806800S82B) 109
5.4.2 DSP-FPGA
The DSP-FPGA is the main control unit on the DSP cluster. It controls all DSP functionality
including the power sequencing. The DSP-FPGA is connected to Glue-Logic FPGA via SPI
interface.
The total count of I/O pins is 207. The table below lists the DSP-FPGA signal groups. The
configuration data is stored in the integrated flash device. For update and recovery, the CPU
has access to the configuration device.
5.4.2.1 DSP-FPGA Update
The DSP-FPGA can be updated using JTAG interface, which is connected to the Glue-Logic
FPGA. Then the payload CPU runs a Staple-Player to update the DSP-FPGA. This approach even
works with an empty DSP-FPGA.
5.4.3 Clock Structure
The main clock inputs DLCK_XTALI of each OCT2224M are sourced from an external 25 MHz
clock. They are internally fed to the selected SERDES PLLs which will trigger the clock recovery
engines.
Care has to be taken to avoid stubs for the JTAG-CLK routing.
Table 5-3 DSP Module Clocks
Clock Frequency Generated by Used by
DSP[x]_XTALI 25.000 MHz Clocktree DSP main clock
SBDI_CLK NA BDI Connector or FPGA DSP debug interface