Artesyn ATCA-8330 Installation and Use (April 2015) - Manual (Page 106)

Functional Description
ATCA-8330 Installation and Use (6806800S82B) 106
The OCT2224M is composed of 24 Opus2 cores. Opus2 is a low-power, high-performance DSP
core. The Opus2 core offers the following features.
 144 Kb of L1 memory per core
 Rich instruction set
5.4.1.1 DDR3 Memory Subsystem
The 32-bit DDR memory controller is used as interface to JEDEC DDR3 SDRAM devices. The
interface is designed to sustain a throughput of 4.32 GB/s at a 1080 MHz data rate (540 MHz
clock rate). Twin-die devices are not supported.
The DSP memory on the ATCA-8330 can comprise of two DDR3 x16 devices per DSP and runs
with 540 MHz currently. The memory access will be 32 bits wide. The default memory is 512
MB.
5.4.1.2 High-speed I/O Subsystems
The High-speed I/O peripherals connect to the DSP directly, but external memory connects via
high-speed buffer managers of the DSP Satellite busses.
PCIe, Serial RapidIO and Ethernet physical interfaces are multiplexed onto 4 SERDES pairs. The
physical pins can be configured for various uses (for example, GPIOs), or can be disabled to save
power. Actual pin configurations are determined by strapping or established by the boot
image.
5.4.1.3 Ethernet MAC Engines
The OCT2224M device has 4 Ethernet MAC engines all running in SGMII mode, supporting
10/100/1000-Mbps data transfer rates. The Ethernet MAC engine supports:
 Half-duplex operation (CSMA/CD) and full-duplex operation (IEEE 802.3x flow control).
 Standard and Jumbo Ethernet frames with sizes up to 16 KB
The DDR3 memory can be used only when DDR configuration is obtained from the boot
image.