Artesyn ATCA-8330 Installation and Use (April 2015) - Manual (Page 132)

Intelligent Peripheral Management Controller
ATCA-8330 Installation and Use (6806800S82B) 132
 Failsafe
 Local System Event Log (SEL)
The IPMC at the front board is acting like a carrier IPMC. It creates a SDR repository providing
direct access to all sensors within the system. The IPMC is implemented as the managed FRU
#0.
The Payload host CPU communicates with the IPMC using the Keyboard Controller Style (KCS)
interface of the H8S. The FRU inventory, SEL events, and the SDR information are stored in
external I2C EEPROMS. This enables post-mortem analysis when the system processor
becomes disabled.
IPMB buffers on both IPMB-0 busses are used to isolate a faulty IPMB bus from the backplane.
The IPMC can access the Glue Logic FPGA Register via SPI Bus and the Power CPLD Register via
the private I2C bus. This enhances the capabilities of the IPMC. The Glue Logic FPGA can be
used to monitor the CPU status, the Payload reset cause and to control the boot bank
selection. The Power CPLD controls the enabling and monitoring of power good signals from
all on-board power converters.