Altera RLDRAM II Controller MegaCore Function - Manual (Page 58)

3–14 MegaCore Version 9.1 Altera Corporation
RLDRAM II Controller MegaCore Function User Guide November 2009
Compile the Example Design
Compile the
Example Design Before the Quartus II software compiles the example design it runs the IP
Toolbench-generated Tcl constraints script,
auto_add_rldramii_constraints.tcl
, which calls the
add_constraints_for_ .tcl script for each variation in your
design. The add_constraints_for_.tcl script checks for
any previously added constraints, removes them, and then adds
constraints for that variation.
The constraints script analyzes and elaborates your design, to
automatically extract the hierarchy to your variation. To prevent the
constraints script analyzing and elaborating your design, turn on Enable
Hierarchy Control
in the wizard, and enter the correct hierarchy path to
your datapath (refer to step 13 on page 3–6 ).
When the constraints script runs, it creates another script,
remove_constraints_for_
.tcl, which you can use to
remove the constraints from your design.
To compile the example instance, follow these steps:
1. Choose Start Compilation (Processing menu), which runs the add
constraints scripts, compiles the example design, and performs
timing analysis.
2. View the Timing Analyzer to verify your design meets timing.
If the compilation does not reach the frequency requirements, follow
these steps:
1. Choose Settings (Assignments menu).
2. Expand Analysis and Synthesis Settings in the category list.
3. Select Speed in Optimization Technique.
4. Expand Fitter Settings.
5. Turn on Optimize Hold Timing and select All Paths.
6. Turn on Fast-corner timing.
7. Click OK.
8. Re-compile the example design by choosing Start Compilation
(Processing menu).