Altera RLDRAM II Controller MegaCore Function - Manual (Page 51)

Altera Corporation MegaCore Version 9.1 3–7
November 2009 RLDRAM II Controller MegaCore Function User Guide
Getting Started
Figure 3–2. System Naming
14. IP Toolbench uses a prefix (for example, rldramii_) for the names of
all memory interface pins. Enter a prefix for all memory interface
pins associated with this custom variation.
15. Enter the pin loading for the FPGA pins.
1
You must enter suitable values for the pin loading, because
the values affect timing.
16. Click Finish.
Step 2: Constraints
To choose the constraints for your device, follow these steps:
1. Click Step 2: Constraints in IP Toolbench.
2. Choose the positions on the device for each of the RLDRAM II byte
groups. To place a byte group, select the byte group in the drop-
down box at your chosen position.
1
The floorplan matches the orientation of the Quartus II
floorplanner. The layout represents the die as viewed from
above. A byte group consists of data (DQ) pins for CIO
devices; or data (Q) pins for SIO devices, and a data strobe
signal (DQS) pin. The number of data pins per byte group
matches your choice of DQ (or Q) per DQS.
RLDRAM II
Datapath
Other Logic
PLL
RLDRAM II
Interface
example_top
Example Top-Level Design
my_rldram
RLDRAM II Controller
my_system
System
my_sub_system
Subystem