Altera RLDRAM II Controller MegaCore Function - Manual (Page 52)

3–8 MegaCore Version 9.1 Altera Corporation
RLDRAM II Controller MegaCore Function User Guide November 2009
RLDRAM II Controller Walkthrough
Step 3: Set Up Simulation
An IP functional simulation model is a cycle-accurate VHDL or Verilog
HDL model produced by the Quartus II software. The model allows for
fast functional simulation of IP using industry-standard VHDL and
Verilog HDL simulators.
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You may only use these simulation model output files for
simulation purposes and expressly not for synthesis or any
other purposes. Using these models for synthesis will create a
nonfunctional design.
To generate an IP functional simulation model for your MegaCore
function, follow these steps:
1. Click Step 3: Set Up Simulation in IP Toolbench.
2. Turn on Generate Simulation Model.
3. Choose the language in the Language list.
4. Some third-party synthesis tools can use a netlist that contains only
the structure of the MegaCore function, but not detailed logic, to
optimize performance of the design that contains the MegaCore
function. If your synthesis tool supports this feature, turn on
Generate netlist
.
5. Click OK.
Step 4: Generate
To generate your MegaCore function, click Step 4: Generate in IP
Toolbench.