Altera RLDRAM II Controller MegaCore Function - Manual (Page 57)

Altera Corporation MegaCore Version 9.1 3–13
November 2009 RLDRAM II Controller MegaCore Function User Guide
Getting Started
11. Add the testbench files. In the File name field browse to the location
of the RLDRAM II model and the testbench, <project name>_tb, click
OK
and click Add.
12. Click OK.
13. Click OK.
14. On the Tools menu point to EDA Simulation Tool and click Run
EDA RTL Simulation .
Edit the PLL The IP Toolbench-generated example design includes a PLL, which has
an input to output clock ratio of 1:1 and a clock frequency that you
entered in IP Toolbench. In addition, IP Toolbench correctly sets all the
phase offsets of all the relevant clock outputs for your design. You can
edit the PLL input clock to make it conform to your system requirements.
If you re-run IP Toolbench and wish to save your PLL edits, turn off
Update example design system PLL
.
1
If you turn off Enable DQS mode, IP Toolbench generates a
second PLL—the fedback PLL. You need not edit the fedback
PLL.
f
For more information on the PLL, refer to “PLL Configuration” on
page 2–12 .
To edit the example PLL, follow these steps:
1. Choose MegaWizard Plug-In Manager (Tools menu).
2. Select Edit an existing custom megafunction variation and click
Next
.
3. In your Quartus II project directory, for VHDL choose
rldramii_pll_
<device name>.vhd; for Verilog HDL choose
rldramii_pll_ <device name>.v.
4. Click Next.
5. Edit the PLL parameters in the altpll MegaWizard Plug-In.
f
For more information on the altpll megafunction, refer to the
Quartus II Help or click Documentation in the ALTPLL MegaWizard
Plug-In.