Altera RLDRAM II Controller MegaCore Function - Manual (Page 26)

2–16 MegaCore Version 9.1 Altera Corporation
RLDRAM II Controller MegaCore Function User Guide November 2009
Interfaces
f
For more details on how to run the simulation script, see “Simulate the
Example Design” on page 3–11 .
Constraints
The constraints scripts set the following constraints:
■ Sets IO standards:
● 1.5 or 1.8-V HSTL voltage selection
● Address and command—HSTL Class I
● Data CIO mode—HSTL Class II
● Data SIO mode—HSTL Class I
■ Sets output capacitance
■ Places data pins as per selection in pin placement constraints floor
plan. Allows automatic placement for DQS and non-DQS modes
■ Places all DM pins
■ Sets up correct output enable groups
■ Sets rldramii_a_0, rldramii_ba_0, rldramii_cs_n_0,
rldramii_ref_n
_0 and rldrainii_we_n_0 as fast output
registers (see note 1 in Table 2–5 )
■ Sets rldramii_qk[] non-global signal in DQS capture mode
■ Add Hold Relationship and Setup Relationship to all I/O ports.
Interfaces This section describes the following RLDRAM II commands:
■ Initialization
■ Writes
■ Reads
■ Refreshes
Initialization
The control logic initializes the RLDRAM II devices. During initialization
the mode register is set and each bank is refreshed in turn. IP Toolbench
sets the following RLDRAM II initialization features:
■ On-die termination (ODT)
■ Impedance matching resistor
■ DLL enable
■ RLDRAM II configuration
Figure 2–11 shows the initialization sequence.