Altera RLDRAM II Controller MegaCore Function - Manual (Page 3)

Altera Corporation MegaCore Version 9.1 iii
Contents
Chapter 1. About This MegaCore Function
Release Information ............................................................................................................................... 1–1
Device Family Support ......................................................................................................................... 1–1
Features ................................................................................................................................................... 1–2
General Description ............................................................................................................................... 1–2
OpenCore Plus Evaluation .............................................................................................................. 1–4
Performance and Resource Utilization ............................................................................................... 1–4
Chapter 2. Functional Description
Block Description ................................................................................................................................... 2–1
Control Logic .................................................................................................................................... 2–2
Datapath ............................................................................................................................................ 2–3
OpenCore Plus Time-Out Behavior ............................................................................................. 2–12
Device-Level Configuration ............................................................................................................... 2–12
PLL Configuration ......................................................................................................................... 2–12
Example Design .............................................................................................................................. 2–14
Constraints ...................................................................................................................................... 2–16
Interfaces ............................................................................................................................................... 2–16
Initialization .................................................................................................................................... 2–16
Writes ............................................................................................................................................... 2–17
Reads ................................................................................................................................................ 2–19
Refreshes .......................................................................................................................................... 2–21
Signals ................................................................................................................................................... 2–22
Parameters ............................................................................................................................................ 2–28
Memory ............................................................................................................................................ 2–29
Timing .............................................................................................................................................. 2–31
Project Settings ................................................................................................................................ 2–32
MegaCore Verification ........................................................................................................................ 2–33
Simulation Environment ............................................................................................................... 2–33
Hardware Testing ........................................................................................................................... 2–33
Chapter 3. Getting Started
Design Flow ............................................................................................................................................ 3–1
RLDRAM II Controller Walkthrough ................................................................................................. 3–2
Create a New Quartus II Project .................................................................................................... 3–3
Launch IP Toolbench ....................................................................................................................... 3–4
Step 1: Parameterize ......................................................................................................................... 3–5
Step 2: Constraints ............................................................................................................................ 3–7
Step 3: Set Up Simulation ................................................................................................................ 3–8
Step 4: Generate ................................................................................................................................ 3–8
Simulate the Example Design ............................................................................................................ 3–11