Altera RLDRAM II Controller MegaCore Function - Manual (Page 22)

2–12 MegaCore Version 9.1 Altera Corporation
RLDRAM II Controller MegaCore Function User Guide November 2009
Device-Level Configuration
of control_rdata[], which means different bit ranges of the
control_rdata[]
are associated with different capture_clk[]
signals.
1 Figure 2–8 is a specific example but the mapping and clock
association applies to any RLDRAM II controller interface and
memory configuration.
OpenCore Plus Time-Out Behavior
OpenCore Plus hardware evaluation can support the following two
modes of operation:
■ Untethered—the design runs for a limited time
■ Tethered—requires a connection between your board and the host
computer. If tethered mode is supported by all megafunctions in a
design, the device can operate for a longer time or indefinitely
All megafunctions in a device time out simultaneously when the most
restrictive evaluation time is reached. If there is more than one
megafunction in a design, a specific megafunction’s time-out behavior
may be masked by the time-out behavior of the other megafunctions.
1
For MegaCore functions, the untethered time out is 1 hour; the
tethered time out value is indefinite.
Your design stops working after the hardware evaluation time expires
and the controller issues no read commands at the memory interface.
f
For more information on OpenCore Plus hardware evaluation, see
“OpenCore Plus Evaluation” on page 1–4 and AN 320: OpenCore Plus
Evaluation of Megafunctions .
Device-Level
Configuration This section describes the following topics:
■ “PLL Configuration” on page 2–12
■ “Example Design” on page 2–14
■ “Constraints” on page 2–16
PLL Configuration
IP Toolbench creates up to two example PLLs in your project directory,
which you can parameterize to meet your exact requirements. IP
Toolbench generates the example PLLs with an input to output clock ratio
of 1:1 and a clock frequency you entered in IP Toolbench. In addition IP
Toolbench sets the correct phase outputs on the PLLs’ clocks. You can