Altera RLDRAM II Controller MegaCore Function - Manual (Page 17)

Altera Corporation MegaCore Version 9.1 2–7
November 2009 RLDRAM II Controller MegaCore Function User Guide
Functional Description
Figure 2–4. DQS Group Block Diagram—DQS Mode, CIO Devices Note (1) , (2) , (3)
Notes to Figure 2–4 :
(1) This figure shows the logic for one DQ output only.
(2) All clocks are clk, unless marked otherwise.
(3) Bus width W is dependent on the DQ per DQS parameter.
(4) Invert combout of the I/O element (IOE) for the dqs pin before feeding in to inclock of the IOE for the DQ pin.
This inversion is automatic if you use an altdq megafunction for the DQ pins.
Figure 2–5 on page 2–8 shows the Stratix II series and HardCopy II
devices DQS group block diagram (DQS mode, SIO devices).
DQS
DQS Delay
Q D
Q D Q D
D
Q
Q Q
D Q
D
D
Q
D Q
control_wdata
DQ
write_clk
control_doing_wr
control_rdata
dq_capture_clk
dq_oe
0
1
2W
2W
W
W
W
W
D
EN
EN
control_wdata_valid
capture_clk
Note 4