Altera RLDRAM II Controller MegaCore Function - Manual (Page 11)

Altera Corporation MegaCore Version 9.1 2–1
November 2009
2. Functional Description
Block
Description Figure 2–1 shows the RLDRAM II Controller MegaCore function block
diagram.
Figure 2–1. RLDRAM II Controller Block Diagram Note (1) , (2)
Notes to Figure 2–1 :
(1) You can edit the rldramii_ prefix in IP Toolbench.
(2) The default signal is <signal>_0. When you specify additional address and command busses, both <signal>_0 and
<signal>_1 are present.
(3) Non-DQS mode only.
(4) DQS mode only.
Control Logic
(Encrypted)
RLDRAM II Controller
clk
write_clk
addr_cmd_clk
non_dqs_
capture_clk ( Note 3)
reset_clk_n
reset_addr_cmd_clk_n
reset_read_clk_n[]
capture_clk[] ( Note 4)
dqs_delay_ctrl[] ( Note 4)
local_addr[]
local_bank_addr[]
local_dm[]
local_read_req
local_refresh_req
local_wdata[]
local_write_req
local_init_done
local_rdata[]
local_rdata_valid[]
local_wdata_req
Datapath
rldramii_dq[]
rldramii_q[]
rldramii_qk[]
rldramii_qvld[]
rldramii_a_0[]
rldramii_ba_0[]
rldramii_clk[]
rldramii_clk_n[]
rldramii_cs_n_0
rldramii_d[]
rldramii_dm[]
rldramii_ref_n_0
rldramii_we_n_0