Altera RLDRAM II Controller MegaCore Function - Manual (Page 55)

Altera Corporation MegaCore Version 9.1 3–11
November 2009 RLDRAM II Controller MegaCore Function User Guide
Getting Started
Simulate the
Example Design This section describes the following simulation techniques:
■ Simulate with IP Functional Simulation Models
■ Simulating in Third-Party Simulation Tools Using NativeLink
Simulate with IP Functional Simulation Models
You can simulate the example design using the IP Toolbench-generated IP
functional simulation models. IP Toolbench generates a VHDL or Verilog
HDL testbench for your example design, which is in the testbench
directory in your project directory.
f
For more information on the testbench, refer to “Example Design” on
page 2–14 .
You can use the IP functional simulation model with any
Altera-supported VHDL or Verilog HDL simulator. To simulate the
example design with the ModelSim
® simulator, follow these steps:
1. Obtain a memory model that matches your chosen parameters and
save it to the <directory name>\testbench directory. For example,
you can download a RLDRAM II model from the Micron web site at
www.micron.com .
1
Before running the simulation you may also need to edit the
testbench to match the chosen RLDRAM II model.
2. Start the ModelSim-Altera simulator.
3. Change your working directory to your IP Toolbench-generated file
directory <directory name>\testbench\modelsim.
4. To simulate with an IP functional simulation model simulation, type
the following command:
source _vsim.tcl r
1
Before running the simulation, you may have to edit the
set memory model
parameter in the
name>_vsim.tcl file to match the selected RLDRAM II
model.
5. For a gate-level timing simulation (VHDL or Verilog HDL
ModelSim output from the Quartus II software), type the following
commands:
set use_gate_model 1 r