Altera RLDRAM II Controller MegaCore Function - Manual (Page 53)

Altera Corporation MegaCore Version 9.1 3–9
November 2009 RLDRAM II Controller MegaCore Function User Guide
Getting Started
Table 3–1 describes the generated files and other files that may be in your
project directory. The names and types of files specified in the IP
Toolbench report vary based on whether you created your design with
VHDL or Verilog HDL
Table 3–1. Generated Files (Part 1 of 2) Note (1) , (2) , (3)
Filename Description
<variation name>.vhd, or .v A MegaCore function variation file, which defines a
VHDL or Verilog HDL description of the custom
MegaCore function. Instantiate the entity defined by this
file inside of your design. Include this file when compiling
your design in the Quartus II software.
<variation name>.cmp A VHDL component declaration file for the MegaCore
function variation. Add the contents of this file to any
VHDL architecture that instantiates the MegaCore
function.
<variation name>.bsf Quartus II symbol file for the MegaCore function
variation. You can use this file in the Quartus II block
diagram editor.
<variation name>.sdc A Synopsys Design Constraints (SDC) file. Use this SDC
file with the DDR timing wizard (DTW)-generated SDC
file when using TimeQuest. You must copy the contents
of this file into the DTW-generated SDC file, so the
example design has the correct timing constraints when
using TimeQuest.
altera_vhdl_support.vhd A VHDL package that contains functions for the
generated entities. This file may be shared between
MegaCore functions.
<variation name>_example_driver.vhd or .v Example driver.
.vhd or .v Example design file.
add_constraints_for_.tcl Add constraints script.
rldramii_pll_.vhd or .v System PLL.
rldramii_fbpll_.vhd or .v Fedback PLL.
<variation
name>_auk_rldramii_addr_cmd_reg.vhd or .v Address and command output registers.
<variation name>_auk_rldramii_clk_gen.vhd or .v Memory clock generator.
<variation
name>_auk_rldramii_controller_ipfs_wrapper.vh
d or .v A file that instantiates the controller.
<variation
name>_auk_rldramii_controller_ipfs_wrapper.vh
o or .vo VHDL or Verilog HDL IP functional simulation model.
<variation name>_auk_rldramii_datapath.vhd or .v Datapath.