Altera RLDRAM II Controller MegaCore Function - Manual (Page 32)

2–22 MegaCore Version 9.1 Altera Corporation
RLDRAM II Controller MegaCore Function User Guide November 2009
Signals
Figure 2–16. Single Refresh Command
Signals Table 2–3 shows the system signals.
clk
Local Interface
local_write_req
local_read_req
local_refresh_req
local_addr[]
local_bank_addr[]
local_wdata_req
local_wdata[]
local_dm[]
RLDRAM II Interface
rldramii_clk
rldramii_clk_n
rldramii_cs_n
rldramii_we_n
rldramii_ref_n
rldramii_a[]
rldramii_ba[]
rldramii_dm[]
rldramii_dq[]
rldramii_qk[]
rldramii_qvld[]
A A B B
A A B B
01 23 45 67 01 23 23
00
A B A
A B A
0 1 2 3 4 5 6 7 7
11 11 00
Table 2–3. System Signals (Part 1 of 3)
Name
Width
(Bits)
Direction Description
clk 1 Input System clock for the control logic and
datapath.
write_clk 1 Input Shifted clock that center aligns write data
to the memory.