Altera RLDRAM II Controller MegaCore Function - Manual (Page 16)

2–6 MegaCore Version 9.1 Altera Corporation
RLDRAM II Controller MegaCore Function User Guide November 2009
Block Description
Pipeline Registers
IP Toolbench can insert pipeline registers into the datapath to help meet
timing at higher frequencies. IP Toolbench offers the following pipeline
options:
■ Insert address and command and write data pipeline registers. The
pipeline depth is the same for the write-data path and the address
and command path. The write data and address and command
pipeline registers are clocked off the system clock.
■ Insert read data and QVLD pipeline registers. The pipeline depth is
the same for the read-data path and the QVLD path. The read data
and QVLD pipeline registers are clocked off the clock that captures
the read data—the delayed rldramii_qk[] signal in DQS mode;
the external capture clock in non-DQS mode.
DQS Group
The datapath instantiates one or more DQS groups, which generates
write data, rldramii_dq[] (CIO devices), or rldramii_d[] (SIO
devices) and captures read data rldramii_dq[] (CIO devices), or
rldramii_q[]
(SIO devices). The IP Toolbench DQ per DQS (CIO
devices) or Q per DQS (SIO devices) parameter determines the DQS
group width. For example, if DQ per DQS is 9 bits, the
control_wdata[]
and control_rdata[] signals are 18-bits wide. To
build larger widths, the datapath instantiates multiple DQS group
modules to increase the data-bus width in increments of DQ per DQS (or
Q per DQS
) bits.
1
The datapath generates the DM output, rldramii_dm[], in the
DM group module. It generates the DM output in the same way
as the write data.
1
The datapath captures the QVLD input, rldramii_qvld[], in
the QVLD group module. The rldramii_qvld[] signal is
captured in the same way that the DQS group module captures
the read data. In DQS mode, the delayed rldramii_qk[]
captures rldramii_qvld[]; in non-DQS mode, the external
clock captures rldramii_qvld[].
Figure 2–4 on page 2–7 shows the Stratix II series and HardCopy II
devices DQS group block diagram (DQS mode, CIO devices).