Altera RLDRAM II Controller MegaCore Function User Manual
Page 23
Altera Corporation
MegaCore Version 9.1
2–13
November 2009
RLDRAM II Controller MegaCore Function User Guide
Functional Description
edit the PLLs to meet your requirements with the altpll MegaWizard
TM
Plug-In. IP Toolbench overwrites your PLLs in your project directory
unless you turn off Update example design system PLL.
The external clocks are generated using standard I/O pins in double data
rate I/O (DDIO) mode (using the altddio_out megafunction). This
generation matches the way in which the write data is generated and
allows better control of the skew between the clock and the data to meet
the timing requirements of the RLDRAM II device.
The PLL has the following outputs:
■
Output c0 drives the system clock that clocks most of the controller
including the control logic and datapath.
■
Output c1 drives the write clock that lags the system clock.
■
Output c2 optionally drives the address and command clock.
■
Output c3 drives the DQS DLL clock.
The recommended configuration for implementing the RLDRAM II
controller in Stratix II series and HardCopy II devices is to use a single
enhanced PLL to produce all the required clock signals. No external clock
buffer is required as the Altera device can generate clock signals for the
RLDRAM II devices.
shows the recommended PLL configuration.