Rldram ii controller walkthrough, Rldram ii controller walkthrough –2 – Altera RLDRAM II Controller MegaCore Function User Manual
Page 46
3–2
MegaCore Version 9.1
Altera Corporation
RLDRAM II Controller MegaCore Function User Guide
November 2009
RLDRAM II Controller Walkthrough
1
IP Toolbench is a toolbar from which you quickly and easily
view documentation, specify parameters, and generate all
of the files necessary for integrating the parameterized
MegaCore function into your design.
3.
Implement the rest of your design using the design entry method of
your choice.
4.
Use the IP Toolbench-generated IP functional simulation model to
verify the operation of your design.
f
For more information on IP functional simulation models, refer to the
chapter in volume 3 of
the Quartus II Handbook.
5.
Edit the PLL.
6.
Use the Quartus II software to add constraints to the example
design and compile the example design.
7.
Perform gate-level timing simulation, or if you have a suitable
development board, you can generate an OpenCore Plus
time-limited programming file, which you can use to verify the
operation of the example design in hardware.
8.
Either obtain a license for the RLDRAM II controller MegaCore
function or replace the encrypted RLDRAM II controller control
logic with your own logic and use the clear-text datapath.
1
If you obtain a license for the RLDRAM II controller, you
must set up licensing.
9.
Generate a programming file for the Altera device(s) on your board.
10. Program the Altera device(s) with the completed design.
RLDRAM II
Controller
Walkthrough
This walkthrough explains how to create a RLDRAM II controller
using
the Altera RLDRAM II controller IP Toolbench and the Quartus II
software on a PC. When you are finished generating a custom variation
of the RLDRAM II controller MegaCore function, you can incorporate it
into your overall project.
This walkthrough requires the following steps:
■
“Create a New Quartus II Project” on page 3–3
■