Altera CPRI v6.0 MegaCore Function User Manual
Cpri v6.0 megacore function user guide
Table of contents
Document Outline
- CPRI v6.0 MegaCore Function User Guide
- Contents
- 1. About the CPRI v6.0 IP Core
- 2. Getting Started with the CPRI v6.0 IP Core
- 3. Functional Description
- Interfaces Overview
- CPRI v6.0 IP Core Clocking Structure
- CPRI v6.0 IP Core Reset Requirements
- Start-Up Sequence Following Reset
- AUX Interface
- Direct IQ Interface
- Direct Vendor Specific Access Interface
- Real-Time Vendor Specific Interface
- Direct HDLC Serial Interface
- Direct L1 Control and Status Interface
- Media Independent Interface (MII) to External Ethernet Block
- CPU Interface to CPRI v6.0 IP Core Registers
- Auto-Rate Negotiation
- Extended Delay Measurement
- Deterministic Latency
- CPRI v6.0 IP Core Transceiver and Transceiver Management Interfaces
- Testing Features
- 4. CPRI v6.0 IP Core Signals
- 5. CPRI v6.0 IP Core Registers
- INTR Register
- L1_STATUS Register
- L1_CONFIG Register
- BIT_RATE_CONFIG Register
- PROT_VER Register
- TX_SCR Register
- RX_SCR Register
- CM_CONFIG Register
- CM_STATUS Register
- START_UP_SEQ Register
- START_UP_TIMER Register
- FLSAR Register
- CTRL_INDEX Register
- TX_CTRL Register
- RX_CTRL Register
- RX_ERR Register
- RX_BFN Register
- LOOPBACK Register
- TX_DELAY Register
- RX_DELAY Register
- TX_EX_DELAY Register
- RX_EX_DELAY Register
- ROUND_TRIP_DELAY Register
- XCVR_BITSLIP Register
- A. Differences Between CPRI v6.0 IP Core and CPRI IP Core
- B. Additional Information