Altera CPRI v6.0 MegaCore Function - Manual (Page 86)

Table 4-3: CPRI v6.0 IP Core Management Signals
Clock Name
Direction
Description
cpri_clkout
Output
Main clock signals
cpri_10g_coreclk
Input
reset
Input Main reset signal
cpu_clk
Input
CPU interface
cpu_reset
Input
cpu_address[15:0] Input
cpu_byteenable[3:0]
Input
cpu_read Input
cpu_write Input
cpu_writedata[31:0] Input
cpu_readdata[31:0] Output
cpu_waitrequest Output
cpu_irq Output
state_startup_
seq[2:0]
Output
Start-up sequence interface
With the exception of the
state_l1_synch
signal, these
signals are available only if you turn on Enable start-up
sequence state machine in the CPRI v6.0 parameter editor.
state_l1_synch[2:0]
Output
nego_bitrate_
complete
Input
nego_protocol_
complete
Input
nego_cm_complete
Input
nego_vss_complete
Input
nego_l1_timer_
expired
Input
nego_bitrate_
in[4:0]
Input
Auto-rate negotiation control and status interface
These signals are available only if you turn on Enable auto-
rate negotiation in the CPRI v6.0 parameter editor. nego_bitrate_
out[4:0]
Output
UG-01156
2014.08.18
CPRI v6.0 IP Core Management Interfaces 4-5
CPRI v6.0 IP Core Signals Altera Corporation
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