Altera CPRI v6.0 MegaCore Function User Manual
Page 32
Multiple interfaces control the contents of the outbound CPRI frame control words and data. The CPRI
v6.0 implements the following transmission priorities among these interfaces:
• CPRI frame control words:
1. If the IP core implements the AUX interface, the AUX interface
aux_tx_data
bus, with appropriate
delay, has first priority in filling in the outbound CPRI frame control words.
2. If the IP core does not implement the AUX interface, or the
aux_tx_mask
value associated with the
relevant incoming data blocks the relevant
aux_tx_data
bits, each of the following interfaces, if
implemented, has secondary priority in filling the relevant part of the outbound CPRI frame
control words:
• Real-time vendor specific interface (RTVS)
• Vendor specific interface (VS)
• AxC control information interface (Ctrl_AxC)
3. For any part of the CPRI frame control words not filled in by one of the previous methods, the
transmission-enabled values most recently written to the control transmit table through the full
control word access registers
CTRL_INDEX
and
TX_CTRL
determine the contents of the outbound
CPRI frame control words. If the most recently written word for a CPRI frame position is not
transmission-enabled, no transmission is authorized from the control transmit table to that CPRI
frame position.
4. If none of the previous methods provides the content for a position in the CPRI frame control
word, the following interfaces, if implemented have the lowest priority in filling the relevant part of
the outbound CPRI frame control words:
• Fast control and management (Ethernet) MII interface
• Slow control and management (HDLC) serial interface
• L1 control and status interface
• Dedicated registers that contain or control content for control word positions in the CPRI
frame. For example, the
rx_prot_ver_filter
field of the
PROT_VER
register
• Transmission of special symbols according to the CPRI protocol. For example, K28.5, D16.2, /S/,
or /T/
• CPRI frame I/Q data words:
1. If the IP core implements the AUX interface, the AUX interface
aux_tx_data
bus, with appropriate
delay, has first priority in filling in the outbound CPRI frame I/Q data words.
2. If the IP core does not implement the AUX interface, or the
aux_tx_mask
value associated with the
relevant incoming data blocks the relevant
aux_tx_data
bits, the Direct I/Q interface, if
implemented, has secondary priority in filling the relevant part of the outbound CPRI frame I/Q
data words.
3-2
Interfaces Overview
UG-01156
2014.08.18
Altera Corporation
Functional Description