Altera CPRI v6.0 MegaCore Function User Manual
Page 109
Bits
Field Name
Type
Value on
Reset
Description
20:16
rx_
bitslip_
out
RO
5'b0
Number of bits of delay (bitslip) detected at the receiver word-
aligner. Value can change at frame synchronization, when the
transceiver is resetting. Any K28.5 symbol position change that
occurs when word alignment is activated changes the bitslip
value.
15:6
Reserved
UR0
10'b0
5
tx_
bitslip_
en
RW
1'b0
Enable manual
tx_bitslip_in
updates.
4:0
tx_
bitslip_
in
RW
5'b0
Number of bits of delay (bitslip) the CPRI v6.0 IP core adds at
the CPRI Tx link.
The CPRI line bit rate determines the following maximum
values for this field:
• Maximum value for IP core variations with CPRI line bit
rate 0.6144 Gbps: 9 bits.
• Maximum value for IP core variations with CPRI line bit
rate greater than 0.6144 Gbps: 19 bits.
5-20
XCVR_BITSLIP Register
UG-01156
2015.02.16
Altera Corporation
CPRI v6.0 IP Core Registers
- MAX 10 JTAG (15 pages)
- MAX 10 Power (21 pages)
- Unique Chip ID (12 pages)
- Remote Update IP Core (43 pages)
- Device-Specific Power Delivery Network (28 pages)
- Device-Specific Power Delivery Network (32 pages)
- Hybrid Memory Cube Controller (69 pages)
- ALTDQ_DQS IP (117 pages)
- MAX 10 Embedded Memory (71 pages)
- MAX 10 Embedded Multipliers (37 pages)
- MAX 10 Clocking and PLL (86 pages)
- MAX 10 FPGA (26 pages)
- MAX 10 FPGA (56 pages)
- USB-Blaster II (22 pages)
- GPIO (22 pages)
- LVDS SERDES (27 pages)
- User Flash Memory (33 pages)
- ALTDQ_DQS2 (100 pages)
- Avalon Tri-State Conduit Components (18 pages)
- Cyclone V Avalon-MM (166 pages)
- Cyclone III FPGA Starter Kit (36 pages)
- Cyclone V Avalon-ST (248 pages)
- Stratix V Avalon-ST (286 pages)
- Stratix V Avalon-ST (293 pages)
- DDR3 SDRAM High-Performance Controller and ALTMEMPHY IP (10 pages)
- Arria 10 Avalon-ST (275 pages)
- Avalon Verification IP Suite (224 pages)
- Avalon Verification IP Suite (178 pages)
- FFT MegaCore Function (50 pages)
- DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP (140 pages)
- Floating-Point (157 pages)
- Integer Arithmetic IP (157 pages)
- Embedded Peripherals IP (336 pages)
- JESD204B IP (158 pages)
- Low Latency Ethernet 10G MAC (109 pages)
- LVDS SERDES Transmitter / Receiver (72 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (3 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (80 pages)
- IP Compiler for PCI Express (372 pages)
- Parallel Flash Loader IP (57 pages)
- Nios II C2H Compiler (138 pages)
- RAM-Based Shift Register (26 pages)
- RAM Initializer (36 pages)
- Phase-Locked Loop Reconfiguration IP Core (51 pages)
- DCFIFO (28 pages)