Altera CPRI v6.0 MegaCore Function - Manual (Page 26)

You must connect the external reset controller signals and the CPRI v6.0 IP core reset controller interface
signals according to the following rules. Refer to Integrating Your IP Core in Your Design: Required
External Blocks on page 2-11 for an illustration of the connections.
• Connect the
tx_digitalreset
,
tx_analogreset
,
tx_ready
,
rx_digitalreset
,
rx_analogreset
,
and
rx_ready
output signals of the reset controllers to the
xcvr_tx_digitalreset
,
xcvr_tx_analogreset
,
xcvr_tx_ready
,
xcvr_rx_digitalreset
,
xcvr_rx_analogreset
, and
xcvr_rx_ready
input signals of the CPRI v6.0 IPcore, respectively.
• Connect the
xcvr_rx_is_lockedtodata
output pin of the CPRI v6.0 IP core to the
rx_is_lockedto-
data
input signal of the RX reset controller.
User logic must provide the connections. Refer to the demonstration testbench for example working user
logic including one correct method to instantiate and connect the external reset controllers.
Related Information
• Interface to the External Reset Controller on page 3-47
• Integrating Your IP Core in Your Design: Required External Blocks on page 2-11
Figure illustrates the required connections.
• Altera Transceiver PHY IP Core User Guide
Information about how to configure the Altera Transceiver PHY Reset Controller for your Arria V GZ
or Stratix V design.
• Arria 10 Transceiver PHY User Guide
Information about how to configure the Altera Transceiver PHY Reset Controller for your Arria 10
design.
Adding the Transceiver Reconfiguration Controller
CPRI v6.0 IP cores that target Arria V GZ and Stratix V devices require an external reconfiguration
controller to compile and to function correctly in hardware. CPRI v6.0 IP cores that target Arria 10
devices include a transceiver reconfiguration controller block and do not require an external reconfigura‐
tion controller.
You can use the IP Catalog to generate the Altera Transceiver Reconfiguration Controller IP core.
When you configure the Altera Transceiver Reconfiguration Controller, you must specify the number of
reconfiguration interfaces. The number of reconfiguration interfaces required for the CPRI v6.0 IP core is
two . You can configure your reconfiguration controller with additional interfaces if your design connects
with multiple transceiver IP cores. You can leave other options at the default settings or modify them for
your preference.
You should connect the
reconfig_to_xcvr
and
reconfig_from_xcvr
ports of the CPRI v6.0 IP core to
the corresponding ports of the reconfiguration controller.
You must drive the CPRI v6.0 IP core
reconfig_clk
input port and the Altera Transceiver Reconfigura‐
tion Controller
mgmt_clk_clk
input port from the same clock source. Drive both ports at a clock
frequency in the range of 100–150MHz.
Related Information
• Arria V GZ and Stratix V Transceiver Reconfiguration Interface on page 3-46
• Altera Transceiver PHY IP Core User Guide
For more information about the Altera Transceiver Reconfiguration Controller.
UG-01156
2014.08.18
Adding the Transceiver Reconfiguration Controller 2-15
Getting Started with the CPRI v6.0 IP Core Altera Corporation
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