Altera CPRI v6.0 MegaCore Function User Manual
Page 17
File Name
Description
<my_ip>.svd
Allows HPS System Debug tools to view the register maps of
peripherals connected to HPS within a Qsys system.
During synthesis, the .svd files for slave interfaces visible to System
Console masters are stored in the .sof file in the debug section.
System Console reads this section, which Qsys can query for register
map information. For system slaves, Qsys can access the registers by
name.
<my_ip>.v
or
<my_ip>.vhd
HDL files that instantiate each submodule or child IP core for
synthesis or simulation.
mentor/
Contains a ModelSim
®
script
msim_setup.tcl
to set up and run a
simulation.
aldec/
Contains a Riviera-PRO script
rivierapro_setup.tcl
to setup and run a
simulation.
/synopsys/vcs
/synopsys/vcsmx
Contains a shell script
vcs_setup.sh
to set up and run a VCS
®
simulation.
Contains a shell script
vcsmx_setup.sh
and
synopsys_ sim.setup
file to
set up and run a VCS MX
®
simulation.
/cadence
Contains a shell script
ncsim_setup.sh
and other setup files to set up
and run an NCSIM simulation.
/submodules
Contains HDL files for the IP core submodule.
<child IP cores>/
For each generated child IP core directory, Qsys generates
/synth
and
/
sim
sub-directories.
2-6
Files Generated for Altera IP Cores
UG-01156
2014.08.18
Altera Corporation
Getting Started with the CPRI v6.0 IP Core