Altera CPRI v6.0 MegaCore Function User Manual
Page 63
RX MII Signals
Signal Name
Direction
Description
mii_rxreset
Input
Resets the MII receiver interface and FIFO read logic. This
reset signal is active low.
mii_rxdv
Output
Ethernet receive data valid. Indicates the presence of valid
data or initial K nibble on
cpri_mii_rxd[3:0]
.
mii_rxer
Output
Ethernet receive error. Indicates an error in the current
nibble of
cpri_mii_rxd
or indicates that the CPRI link is
not initialized, and therefore an error might be present in
the frame being transferred to the external Ethernet block.
This signal is de-asserted at reset, and asserted after reset
until the CPRI v6.0 IP core achieves frame synchroniza‐
tion.
mii_rxd[3:0]
Output
Ethernet receive nibble data. Data bus for data from the
CPRI v6.0 IP core to the external Ethernet block. All bits
are de-asserted during reset, and all bits are asserted after
reset until the CPRI v6.0 IP core achieves frame synchro‐
nization.
TX MII Signals
Signal Name
Direction
Description
mii_txclk
Input
Clocks the MII transmitter interface. You must drive this
clock at the frequency of 25 MHz to achieve the 100 Mbps
bandwidth required for this interface.
mii_txreset
Input
Resets the MII transmitter interface and FIFO write logic.
This signal is active low.
mii_txen
Input
Valid signal from the external Ethernet block, indicating
the presence of valid data on
mii_tx[3:0]
. This signal is
also asserted while the CPRI v6.0 MII transmitter block
inserts J and K nibbles in the data stream to form the start-
of-packet symbol. This signal is typically asserted one
cycle after
mii_txrd
is asserted. After the first cycle
following the assertion of
mii_txrd
, if
mii_txen
is not yet
asserted, the CPRI v6.0 MII transmitter module inserts
Idle cycles until the first cycle in which
mii_txen
is
asserted. If
mii_txen
is asserted and subsequently de-
asserted while
mii_txrd
remains asserted, the CPRI v6.0
MII transmitter module inserts the end-of-packet
sequence.
mii_txer
Input
Ethernet transmit coding error. When this signal is
asserted, the CPRI v6.0 IP core inserts an Ethernet HALT
symbol in the data it passes to the CPRI link.
mii_txd[3:0]
Input
Ethernet transmit nibble data. The data transmitted from
the external Ethernet block to the CPRI v6.0 IP core, for
transmission on the CPRI link. This input bus is synchro‐
nous to the rising edge of the
mii_txclk
clock.
UG-01156
2014.08.18
Media Independent Interface (MII) to External Ethernet Block
3-33
Functional Description
Altera Corporation