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Cpri v6.0 ip core supported features, Cpri v6.0 ip core supported features -2 – Altera CPRI v6.0 MegaCore Function User Manual

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CPRI v6.0 IP Core Supported Features

The CPRI v6.0 IP core offers the following features:
• Compliant with the Common Public Radio Interface (CPRI) Specification V6.0 (2013-08-30) Interface

Specification available on the CPRI Industry Initiative website (www.cpri.info).

• Supports radio equipment controller (REC) and radio equipment (RE) module configurations.

• Supports the following CPRI link features:

• Configurable CPRI communication line bit rate (to 0.6144, 1.2288, 2.4576, 3.0720, 4.9152, 6.144,

9.8304, or 10.1376 Gbps) using Altera on-chip high-speed transceivers.

• CPRI line bit rate auto-rate negotiation support.

• Configurable and run-time programmable operation mode: CPRI link master or CPRI link slave.

• Optional scrambling and descrambling at 4.9152, 6.1440, 9.8304, and 10.1376 Gbps.

• Transmitter (Tx) and receiver (Rx) delay measurement and calibration.

• Optional L1 link status and alarm (Z.130.0) control and status monitoring.

• Access to all Vendor Specific data.

• Diagnostic parallel reverse loopback paths.

• Diagnostic serial and parallel forward loopback paths.

• Diagnostic stand-alone slave testing mode.

• Includes the following interfaces:

• Register access interface to external or on-chip processor, using the Altera Avalon

®

Memory-

Mapped (Avalon-MM) interconnect specification.

• Optional auxiliary (AUX) interface for full access to raw CPRI frame. Provides direct access to full

radioframe, synchronizes the frame position with timing references, and enables routing applica‐

tion support from slave to master ports to implement daisy-chain topologies.

• Optional IEEE 802.3 100BASE-X compliant 100Mbps MII for Ethernet frame access.

• Optional direct I/Q access interface enables integration of all user-defined air standard I/Q

mapping schemes.

• Optional vendor specific data access interfaces provide direct access to Vendor Specific (VS),

Control AxC (Ctrl_AxC), and Real-time Vendor Specific (RTVS) subchannels.

• Optional HDLC serial interface provides direct access to slow control and management subchan‐

nels.

• Optional L1 inband interface provides direct access to Z.130.0 link status and alarm control word.

Related Information

CPRI Industry Initiative website

For a detailed specification of the CPRI protocol refer to the CPRI Specification V6.0 (2013-08-30)

Interface Specification available on the CPRI Industry Initiative website.

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CPRI v6.0 IP Core Supported Features

UG-01156

2014.08.18

Altera Corporation

About the CPRI v6.0 IP Core

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